1. Field of the Invention
The present invention relates to a bus cycle timing control circuit for use in a microprocessor, and more specifically to a bus cycle timing controlling circuit for controlling a bus cycle in a data transfer between an external memory or an I/O (input/output) device and a microprocessor.
2. Description of Related Art
In general, a CPU (central processing unit) of a microprocessor is configured to generate a control signal for control a bus used for the transfer of data between the microprocessor and the memory or others. An external device such as a memory or an I/O device carries out the transfer of data through the bus, during a predetermined period of time corresponding to the control signal generated by the CPU.
A low access speed of the external device is compensated for by sending a ready signal to the microprocessor. A bus cycle is started with a request generated from an internal of the microprocessor, and continuous bus cycles are generated with no interval between the bus cycles.
Referring to FIG. 1, there is shown a timing chart illustrating one example of the bus cycle. In FIG. 1, a read/write signal R/W indicates whether the bus cycle being executed is for a reading or for a writing, and a bus cycle start signal BCS shows a start of the bus cycle. In addition, a data strobe signal ST is indicates that the bus cycle is a read/write cycle of data, and a ready signal RY is a control signal for designating whether or not the bus cycle is to be extended. Each of bus cycles BS is composed of a plurality of bus states exemplified by T1, T2, T3, T4, etc., and is carried out in synchronism with a clock CK. An address A shows an address to be accessed by the microprocessor, and data D indicates data to be read or written.
Now, the operation of the bus cycle will be explained with reference to FIG. 1.
In a bus state T1 of a first bus cycle "BUS CYCLE 1", the microprocessor outputs a first address A, and simultaneously brings the read/write signal R/W into a read condition and activates the bus cycle start signal BCS. In a bus state T2, the data strobe signal ST is activated, and the bus cycle start signal BCS is inactivated. In a bus state T3, data D is read out from a memory to the data bus, and the ready signal RY is activated. The microprocessor receives the ready signal RY and fetches the data D from the data bus. In a bus state T4, the microprocessor inactivates the data strobe signal ST, and the memory inactivates the data bus. Thus, one bus cycle is completed.
In the bus state T1 of the second bus cycle "BUS CYCLE 2", the microprocessor outputs the next address A and data D to be written, and simultaneously brings the read/write signal R/W into a write condition and activates the bus cycle start signal BCS. In a bus state T2, the data strobe signal ST is activated, and the bus cycle start signal BCS is inactivated. In a bus state T3, data D on the data bus is written into the memory, and the ready signal RY is activated. The microprocessor receives the ready signal RY. In a bus state T4, the microprocessor inactivates the data strobe signal ST, and removes the data D on the data bus. Thus, another bus cycle is completed.
An LSI (large scaled integrated circuit) for the I/O device can be one of the external devices having a slow access speed. FIG. 2A shows a timing chart illustrating one example of an access operation in a conventional I/O device. In FIG. 2A, both a read control signal and a write control signal are a negative active logic.
Since this type of LSI for the I/O device does not cope with the microprocessor having a high operation speed, it is necessary, as shown in FIG. 2A at the time of the access, to ensure set-up times t.sub.SAR and t.sub.SAW and hold times t.sub.HAR and t.sub.HAW for an address A and a chip select signal CS, set-up times t.sub.DRD and t.sub.SDW for the data, and an access interval t.sub.RV. The access interval t.sub.RV is realized by inserting an instruction independent of an I/O cycle, between continuous access instructions in an actual operation, in the software.
A typical example of the memory is a DRAM (dynamic random access memory). FIG. 2B is a timing chart illustrating one example of an operation of continuous read cycles in a conventional DRAM. In FIG. 2B, a row address strobe signal RAS is a negative active logic, and controls a timing for latching a row address and a timing for reading a row memory cell, and a column address strobe signal CAS is a negative active logic, and controls a timing for latching a column address and a timing for selecting a column memory cell. A row/column address signal ADDR is a multiplexed signal of the row address and the column address.
Now, the procedures for the memory accessing will be described. First, a first half of an address bus of the CPU is given to the DRAM. The row address strobe signal RAS is activated. Next, the remaining half of the address bus is given to the DRAM. A write enable signal WE of a positive active logic is activated, and the column address strobe CAS is activated. An output signal appears on a data output DO. Thereafter, the row address strobe signal RAS and the column address strobe signal CAS are inactivated. The data output DO is brought into a high impedance condition, so that the signal outputting is stopped.
In order to make it easy to couple a memory or I/O device of a low speed to the microprocessor, there has been known a programmable wait controller configured to automatically insert into the bus cycle a wait time (wait state) corresponding to a time period of 0 (zero) clock to any desired number of clocks.
As shown in FIG. 3, this programmable wait controller includes a latch 1 for latching data on an internal data bus, and a counter 8 receiving a clock CK through a NAND gate G.sub.1 for down-counting the received clocks by the number designated by the data latched in the latch 1. When the down-counting reaches the designated number, an output of the counter 8 is supplied to one input of a flipflop composed of NAND gates G.sub.6 and G.sub.7. An output of the flipflop is outputted through AND gates G.sub.4 and G.sub.3 as the ready signal RY. The read signal RD and the write signal WE are inputted to a NAND gate G.sub.5, whose output is connected to an inverter G.sub.2 and the other input of each of the gates G.sub.1, G.sub.3 and G.sub.6. An output of the inverter G.sub.2 is also connected to the counter 8. This programmable wait controller is incorporated in a microprocessor commercially available from NEC Corporation under the tradename mPD70216, and therefore, further explanation will be omitted.
In the shown programmable wait controller, the counter 8 operates to down-count the clock CK from the number stored in the latch circuit 1, and a wait state or states corresponding to the number of the clocks CK counted are generated so as to control an internal ready RY. With this arrangement, a ROM or an I/O device having a fixed access time can be connected to the microprocessor through only a simple decode circuit.
Some types of microprocessors have been configured to automatically set an interval between continuous I/O bus cycles. For example, this corresponds to insertion of a bus cycle having a fixed length of three clocks in a continuous access to the low speed I/O device as mentioned above. FIG. 2C illustrates a timing chart of the continuous I/O bus cycle. In FIG. 2C, the bus cycles "BUS CYCLE 1" and "BUS CYCLE 3" are continuous, but a bus cycle "BUS CYCLE 2" composed of three wait states Ti is inserted between the continuous bus cycles "BUS CYCLE 1" and "BUS CYCLE 3" for the purpose of the recovery.
As will be apparent from the above, the conventional bus cycle timing control is featured in that the microprocessor is provided with the wait circuit for inserting a fixed wait so as to control the access time in order to cope with a low speed external device such as a memory or an I/O device. However, the external memory and the I/O device prescribe not only the access time but also a recovery time between the bus cycles. Therefore, it is necessary to externally connect a sequencer formed of complicated circuits to insert a continuous access a wait time in order to meet the prescribed values which are different for each of the memory and the I/O device to be coupled. Alternatively, it is necessary to deal with a portion of the wait time generation in a software manner. These are disadvantageous. In the case of dealing with a portion of the wait time generation in a software manner, at each time the clock frequency is changed or the access time of the memory or another to be coupled changes, it is necessary to completely rewrite a portion of the software corresponding to the changed portion. This is also disadvantageous.